1. Field of the Invention
The present invention relates to frequency synthesis and more particularly to fractional phase-locked loop frequency synthesizers.
In many fields, it is necessary to generate wave trains at different frequencies while preserving phase coherence between wave trains of the same frequency, i.e. it is necessary to preserve one and the same phase shift with respect to a pilot signal, so that it is possible for example to follow its Doppler history.
A phase-locked loop frequency synthesizer consists of a voltage controlled oscillator that is phase-locked to a reference oscillator by means of a phase-locked loop that compares a sub-harmonic of the output signal from the voltage controlled oscillator, obtained by integer division or fractional division, with the signal of the reference oscillator. The division is done by means of a counter-divider with an integer division ratio that is updated at each overflow. As a result of this, the beginning of a wave train is always synchronized with an overflow of the counter-divider which itself occurs during a cycle of the signal of the reference oscillator. The lack of coherence appears for a fractional division ratio for, in this case, the overflows of the counter-divider occur, in relation to the cycles of the signal of the reference oscillator, with a phase shift that develops over a duration equal to the least common multiple of cycles between the signal of the voltage controlled oscillator and that of the reference oscillator.
2. Description of the Prior Art
Present day fractional phase-locked loop frequency synthesizers use a counter-divider with at least two successive integer ratios of division N and N+1 and a modulo P digital accumulator, with an integer increment K that is smaller than P and adjustable. This digital accumulator, whose rate is set by the output signal of the counter-divider, is used to activate the change-over of the division ratio of this counter-divider from N to N+1 and vice versa. The result thereof is that the beginning of a wave train, which coincides with a change in the increment K used to adjust the fractional division ratio, may occur without distinction, during any unspecified overflow of the counter-divider, at several points in the duration corresponding to the least common multiple of cycles between the two signals, with various values of phase shift. This randomness leads to a lack of coherence between wave trains of the same frequency if, in the meantime, the frequency synthesizer has been subjected to a frequency switch.
The present invention is aimed at obtaining fractional phase-locked loop frequency synthesizers capable of generating coherent signals even after a frequency excursion.